IBM's new chip architecture packs nearly 100 billion transistors onto a chip the size of a human fingernail — nearly double the transistor density of the company's previous generation of technology. The new technology will enable faster, more energy-efficient chips for AI data centers.
IBM's new chip architecture packs nearly 100 billion transistors onto a chip the size of a human fingernail — nearly double the transistor density of the company's previous generation of technology. The new technology will enable faster, more energy-efficient chips for AI data centers.
Modern developers faced a problem: there is no way to physically reduce the size of chip parts (transistors) - if they are made smaller than 1 nanometer, they will simply stop working stably. Therefore, IBM did not go the way of reduction, but a new three-dimensional layout.
Instead of placing transistors on a plane next to each other, the new “nanostack” architecture staggered them and stacked them vertically (one on top of the other). This allows for a huge number of elements to fit into the same area.
The smallest "brick" of this architecture is two transistors, which are placed on top of each other and firmly connected.
Each of these two transistors consists of three ultrathin horizontal layers called nanosheets. Each sheet is just 5 nanometers thick (a tiny distance, equivalent to about 15 rows of silicon atoms), and the gap between them is about 9 nanometers.
Although the physical dimensions of the chip are not smaller than 1 nanometer, IBM’s dense architecture has allowed it to pack nearly 100 billion transistors into a processor the size of a human fingernail. This has provided a significant boost in speed and energy efficiency for AI data centers that theorists would only expect from a hypothetical “sub-nanometer” chip. Hence the marketing name for the process technology — “7 angstroms” (or 0.7 nm), although it has no relation to the actual physical dimensions.
The nanostack architecture can deliver 50% more computing power or 70% more energy efficiency compared to the company's previous generation of 2-nanometer chips.
Additionally, the nanostack architecture enables a 40% improvement in the scalability of static random access memory (SRAM). SRAM provides fast but power-intensive read and write operations that are critical for many AI applications.
This memory improvement is made possible by the staggered channel design of SRAM bit cells. These cells are memory storage elements, each consisting of six transistors; this architecture reduces the overall height of the cell by 40% and allows more SRAM to be "squeezed" into the same chip area.
This is likely to be great news for chip designers looking to support AI workloads, given how dramatically SRAM scaling has slowed in recent generations of chip technology.
